CS43303: Digital System Testing And Testable Design

CS43303
Course name	Digital System Testing And Testable Design
Offered by	Computer Science & Engineering
Credits	5
L-T-P	3-0-3
Previous Year Grade Distribution
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Semester	Autumn

Syllabus

Syllabus mentioned in ERP

Physical faults and their modeling. Fault equivalence and dominance; fault collapsing. Fault simulation: parallel, deductive and concurrent techniques; critical path tracing. Test generation for combinational circuits: Boolean difference, D-algorithm, Podem, etc. Exhaustive, random and weighted test pattern generation; aliasing and its effect on fault coverage. PLA testing: cross-point fault model, test generation, easily testable designs. Memory testing: permanent, intermittent and pattern-sensitive faults; test generation. Delay faults and hazards; test generation techniques. Test pattern generation for sequential circuits: time-frame expansion method, ad-hoc and structures techniques, scan path and LSSD, boundary scan. Built-in self-test techniques. Testing issues in embedded core based systems.References1.N. K. Jha and S. Gupta, Testing of Digital Systems, Cambridge University Press.2.M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing, Kluwer Academic Publishers.3.M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design, Wiley-IEEE Press.4.P. H. Bardell, W. H. McAnney and J. Savir, Built-in Test for VLSI: Pseudorandom Techniques, Wiley Interscience.5.P. K. Lala, Fault Tolerant and Fault Testable Hardware Design, Prentice-Hall.6.A. Krstic and K-T Cheng, Delay Fault Testing for VLSI Circuits, Kluwer Academic Publishers.7.A. Osseiran (Ed.), Analog and Mixed Signal Boundary Scan, Kluwer Academic Publishers.