CS60089: Testing And Verification Of Circuits

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CS60089
Course name Testing And Verification Of Circuits
Offered by Computer Science & Engineering
Credits 4
L-T-P 3-1-0
Previous Year Grade Distribution


3
2
3




EX A B C D P F
Semester Autumn


Syllabus

Syllabus mentioned in ERP

Physical faults and their modeling. Fault equivalence and dominance; fault collapsing. Fault simulation: parallel, deductive and concurrent techniques; critical path tracing. Test generation for combinational circuits: Boolean difference, D-algorithm, Podem, etc. Exhaustive, random and weighted test pattern generation; aliasing and its effect on fault coverage. PLA testing: cross-point fault model, test generation, easily testable designs. Memory testing: permanent, intermittent and pattern-sensitive faults; test generation. Delay faults and hazards; test generation techniques. Test pattern generation for sequential circuits: ad-hoc and structures techniques, scan path and LSSD, boundary scan. Built-in self-test techniques. Verification: logic level (combinational and sequential circuits), RTL-level (data path and control path). Verification of embedded systems. Use of formal techniques: decision diagrams, logic-based approaches.


Concepts taught in class

Student Opinion

How to Crack the Paper

Classroom resources

Additional Resources

Time Table

Day 8:00-8:55 am 9:00-9:55 am 10:00-10:55 am 11:00-11:55 am 12:00-12:55 pm 2:00-2:55 pm 3:00-3:55 pm 4:00-4:55 pm 5:00-5:55 pm
Monday
Tuesday
Wednesday CSE-120
Thursday CSE-120
Friday CSE-120 CSE-120