EC60291: Architectural Design Of Ics
| EC60291 | |||||||||||||||||||||||||||
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| Course name | Architectural Design Of Ics | ||||||||||||||||||||||||||
| Offered by | Electronics & Electrical Communication Engineering | ||||||||||||||||||||||||||
| Credits | 3 | ||||||||||||||||||||||||||
| L-T-P | 3-0-0 | ||||||||||||||||||||||||||
| Previous Year Grade Distribution | |||||||||||||||||||||||||||
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| Semester | Autumn | ||||||||||||||||||||||||||
Syllabus[edit | edit source]
Syllabus mentioned in ERP[edit | edit source]
Pre-requisites: EC30004Introduction: VLSI Design flow, general design methodologies; Mapping algorithms into Architectures: Signal flow graph, data dependences, datapath synthesis, control structures, critical path and worst case timing analysis, concept of hierarchical system design; Datapath elementa: Datapath design philosophies, fast adder, multiplier, driver etc., datapath optimization, application specific combinatorial and sequential circuit design, CORDIC unit; Pipeline and parallel architectures: Architecture for real time systems, latency and throughput related issues, clocking strategy, power conscious structures, array architectures; Control strategies: Hardware implementation of various control structures, microprogrammed control techniques, VLIW architecture; Testable architecture: Controllability and observability, boundary scan and other such techniques, identifying fault locations, self reconfigurable fault tolerant structures; Treadeoff issues: Optimization with regard to speed, area and power, asynchronous and low power system design, ASIC (application specific integrated circuits) and ASISP (application specific instruction set processors) design;
Concepts taught in class[edit | edit source]
Student Opinion[edit | edit source]
The concepts are the must for the people who are going to start their journey in VLSI(both Analog & VLSI),DSP architectures
Summarizing the concepts(2023-autumn semester) :
- Mapping of algorithmn to architecture.
- Combinational CKT deisgn
- Sequential CKT deisgn
- Multi Function
- Multiplexer Optimization
- Pipleined & parallel structure
- 'Running average' architecture
- Signed Magnitude
- 2's Complement.
- Co-ordinate Rotational Digital Compute(CORDIC) Architecture.
- Multiplier array (Braun's array &Baugh - wooley array)
- Divider(Restoring)
- Systolic Array
- Floating Point adder
- Conditional SUm adder .
- Testing(Reduction of test vectors & Boundary scan technique)
- Fault tolerant reconfigurable architectures.
What concepts are taught in class ,the questions will be framed based on this concepts your aptitude level .
How to Crack the Paper[edit | edit source]
Classroom resources[edit | edit source]
Additional Resources[edit | edit source]
Time Table[edit | edit source]
| Day | 8:00-8:55 am | 9:00-9:55 am | 10:00-10:55 am | 11:00-11:55 am | 12:00-12:55 pm | 2:00-2:55 pm | 3:00-3:55 pm | 4:00-4:55 pm | 5:00-5:55 pm | |
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| Monday | ||||||||||
| Tuesday | ||||||||||
| Wednesday | r302(2023) | F102 | ||||||||
| Thursday | F102/r302(2023) | |||||||||
| Friday | R302(2023) | F102 |