EC60291: Architectural Design Of Ics

EC60291
Course name	Architectural Design Of Ics
Offered by	Electronics & Electrical Communication Engineering
Credits	3
L-T-P	3-0-0
Previous Year Grade Distribution
3 10 7 4 1 1 EX A B C D P F
Semester	Autumn

Syllabus

Syllabus mentioned in ERP

Pre-requisites: EC30004Introduction: VLSI Design flow, general design methodologies; Mapping algorithms into Architectures: Signal flow graph, data dependences, datapath synthesis, control structures, critical path and worst case timing analysis, concept of hierarchical system design; Datapath elementa: Datapath design philosophies, fast adder, multiplier, driver etc., datapath optimization, application specific combinatorial and sequential circuit design, CORDIC unit; Pipeline and parallel architectures: Architecture for real time systems, latency and throughput related issues, clocking strategy, power conscious structures, array architectures; Control strategies: Hardware implementation of various control structures, microprogrammed control techniques, VLIW architecture; Testable architecture: Controllability and observability, boundary scan and other such techniques, identifying fault locations, self reconfigurable fault tolerant structures; Treadeoff issues: Optimization with regard to speed, area and power, asynchronous and low power system design, ASIC (application specific integrated circuits) and ASISP (application specific instruction set processors) design;

Concepts taught in class

Student Opinion

The concepts are the must for the people who are going to start their journey in VLSI(both Analog & VLSI),DSP architectures

Summarizing the concepts(2023-autumn semester) :

1. Mapping of algorithmn to architecture.
2. Combinational CKT deisgn
3. Sequential CKT deisgn
4. Multi Function
5. Multiplexer Optimization
6. Pipleined & parallel structure
7. 'Running average' architecture
8. Signed Magnitude
9. 2's Complement.
10. Co-ordinate Rotational Digital Compute(CORDIC) Architecture.
11. Multiplier array (Braun's array &Baugh - wooley array)
12. Divider(Restoring)
13. Systolic Array
14. Floating Point adder
15. Conditional SUm adder .
16. Testing(Reduction of test vectors & Boundary scan technique)
17. Fault tolerant reconfigurable architectures.

What concepts are taught in class ,the questions will be framed based on this concepts your aptitude level .

Time Table

Day	8:00-8:55 am	9:00-9:55 am	10:00-10:55 am	11:00-11:55 am	12:00-12:55 pm		2:00-2:55 pm	3:00-3:55 pm	4:00-4:55 pm	5:00-5:55 pm
Monday
Tuesday
Wednesday				r302(2023)	F102
Thursday				F102/r302(2023)
Friday	R302(2023)	F102