EC60297: Vlsi Interconnects

EC60297
Course name	VLSI INTERCONNECTS
Offered by	Electronics & Electrical Communication Engineering
Credits	3
L-T-P	3-0-0
Previous Year Grade Distribution
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Semester	{{{semester}}}

Syllabus

Syllabus mentioned in ERP

Pre-requisites: EC30004 Introduction: Moores law, Technological trends, Interconnect scaling, 3D-interconnect view; Interconnect delay modeling: Typical interconnect structure, Extraction of interconnect parameters, modeling interconnect drivers, switch-level RC model, effective capacitance modeling; Interconnection Length Prediction: Rents rule and parameter, Technology extrapolation, performance prediction, Interconnect-power and power modeling; Inductance of Interconnects: Increasing the effects of inductance, skin effect and its influence on resistance and inductance, Partial element equivalent circuit (PEEC) method; Driving interconnect for circuit speed optimization: Evolution of the speed optimization problem, logical effort method, Wire sizing, spacing. Driving RC trees; Crosstalk noise: Crosstalk configuration, DC noise margins, Reasons for high delay uncertainty, switch factor modeling of delay uncertainty, Buffer insertion for noise; Routing topology generation for speed optimization: New approaches in routing topology generation. Width optimization based on separability /monotonicity properties;

Time Table

Day	8:00-8:55 am	9:00-9:55 am	10:00-10:55 am	11:00-11:55 am	12:00-12:55 pm		2:00-2:55 pm	3:00-3:55 pm	4:00-4:55 pm	5:00-5:55 pm
Monday
Tuesday
Wednesday				F101
Thursday					F101
Friday	F101