EC61405: Vlsi For Tele-Communication
| EC61405 | |||||||||||||||||||||||
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| Course name | Vlsi For Tele-Communication | ||||||||||||||||||||||
| Offered by | Electronics & Electrical Communication Engineering | ||||||||||||||||||||||
| Credits | 3 | ||||||||||||||||||||||
| L-T-P | 3-0-0 | ||||||||||||||||||||||
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| Semester | Autumn | ||||||||||||||||||||||
Syllabus[edit | edit source]
Syllabus mentioned in ERP[edit | edit source]
Contents : VLSI design issues for signal processing and communication algorithms. Graphical representation of DSP algorithms, signal flow graph, data flow graph (DFG) and dependence graph (DG), concept of critical path. Retiming, cutset retiming, critical path minimization. Parallel realization by unfolding a DFG, properties of unfolding, retiming for unfolding, bit serial to digit serial and word serial conversions. Area minimization by folding, retiming for folding, folding for delay optimization. Systolic arrays, projection operations on a DG, examples of systolic arrays. Bit level arithmetic structures, efficient multiplier architectures, Booth recoding, CSD, bit serial digital filters, multiplierless realization by distributed arithmetic, redundant arithmetic.
Concepts taught in class[edit | edit source]
Student Opinion[edit | edit source]
How to Crack the Paper[edit | edit source]
Classroom resources[edit | edit source]
Additional Resources[edit | edit source]
Time Table[edit | edit source]
| Day | 8:00-8:55 am | 9:00-9:55 am | 10:00-10:55 am | 11:00-11:55 am | 12:00-12:55 pm | 2:00-2:55 pm | 3:00-3:55 pm | 4:00-4:55 pm | 5:00-5:55 pm | |
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| Monday | F104 | |||||||||
| Tuesday | F104 | F104 | ||||||||
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