CS61068: Cad For Vlsi Design

CS61068
Course name	Cad For Vlsi Design
Offered by	Computer Science & Engineering
Credits	4
L-T-P	3-1-0
Previous Year Grade Distribution
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Semester	Spring

Syllabus

Syllabus mentioned in ERP

Introduction: VLSI design flow, challenges. Verilog/VHDL: introduction and use in synthesis, modeling combinational and sequential logic, writing test benches. Logic synthesis: two-level and multilevel gate-level optimization tools, state assignment of finite state machines. Basic concepts of high-level synthesis: partitioning, scheduling, allocation and binding. Technology mapping. Testability issues: fault modeling and simulation, test generation, design for testability, built-in self-test. Testing SoC s. Basic concepts of verification. Physical design automation. Review of MOS/CMOS fabrication technology. VLSI design styles: full-custom, standard-cell, gate-array and FPGA. Physical design automation algorithms: floor-planning, placement, routing, compaction, design rule check, power and delay estimation, clock and power routing, etc. Special considerations for analog and mixed-signal designs.