EC31004: Vlsi Engg.
| EC31004 | |||||||||||||||||||||||||||
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| Course name | Vlsi Engg. | ||||||||||||||||||||||||||
| Offered by | Electronics & Electrical Communication Engineering | ||||||||||||||||||||||||||
| Credits | 3 | ||||||||||||||||||||||||||
| L-T-P | 3-0-0 | ||||||||||||||||||||||||||
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| Semester | Spring | ||||||||||||||||||||||||||
Syllabus
Syllabus mentioned in ERP
Pre-requisites: EC21007, EC21002 and EC31003Introduction: Design hierarchy, layers of abstraction, integration density and MooreâÂÂs law, VLSI design styles, packaging styles, design automation principles; Fabrication Technology: Basic steps of fabrication, bipolar, CMOS and Bi-CMOS fabrication processes, layout design rules; MOS and Bi-CMOS characteristics and circuits: MOS transistor characteristics, MOS switch and inverter, Bi-CMOS inverter, latch-up in CMOS inverter, super-buffers, propagation delay models, switching delay in logic circuits, CMOS analog amplifier; Logic Design: switch logic, gate restoring logic, various logic families and logic gates, PLA; Dynamic Circuits: Basic concept, noise considerations, charge sharing, cascading dynamic gates, domino logic, np-CMOS logic, clocking schemes; Sequential Circuits: Basic regenerative circuits, bistable circuit elements, CMOS SR latch, clocked latch and flip-flops; Low-power Circuits: low-power designthrough voltage scaling, estimation and optimization of switching activity, reduction of switched capacitance, adiabatic logic circuits; Subsystem Design: design of arithmetic building blocks like adders, multipliers, shifters, area-speed-power tradeoff; Semiconductor Memories: SRAM, DRAM, non-volatile memories; Bipolar ECL Inverter: Features of ECL gate, robustness and noise immunity, logic design in ECL, single-ended and differential ECL gates; Testability of VLSI: Fault models, scan-based techniques, BIST, test vector generation; Physical Design: Brief ideas on partitioning, placement, routing and compaction.