EE60100: Mixed Signal Circuits And Systems On Chip

EE60100
Course name	Mixed Signal Circuits And Systems On Chip
Offered by	Electrical Engineering
Credits	4
L-T-P	3-1-0
Previous Year Grade Distribution
1 1 5 4 6 12 2 EX A B C D P F
Semester	Spring

Syllabus

Syllabus mentioned in ERP

EE60100 Mixed Signal Circuits and Systems on Chip L-T-P: 3-1-0 Credits: 4 Prerequisite: EE60032 Analog Signal ProcessingCOMPARATORSCharacterization of comparators: Analysis and design of a two-stage open-loop comparatorAdvanced comparators: hysteresis, auto-zeroing, push-pullDigital and high-speed comparator topologiesOPERATIONAL TRANSCONDUCTANCE AMPLIFIERSVarious performance characteristics: Differential gain, Common mode gain, CMRR, PSRR, offset voltage, ICMR, Output swing, Input noise, UGF, Slew rate, Settling time, Quiescent power consumption etc.Single Stage OTA Scheme:Telescopic Cascode, Mirrored OTA and Mirrored Cascode OTA, Folded Cascode, Single Stage with Enhanced DC gain. Applications of OTA. DATA CONVERTERSReview of data conversion techniques and terminologyHigh speed digital to analog conversion: segmentation basedHigh resolution data conversion: algorithmic, self-calibrating, etc.Sample and hold amplifiersNoise shaping digital to analog conversionSigma delta analog to digital converters and their implementationTesting of data convertersSYSTEMS ON CHIP (SOC) Introduction to SOC and IP based Design: Classification of IP Cores Digital Subsystem Integration: Buses and Clock distribution Analog Subsystem Integration: DAC, ADC, PLL and high speed I/O Memory Integration: Sense amplifiers and Logic CircuitsOn Chip Bus: Processor local bus and on-chip peripheral bus SOC architectural design: Some case studies (Processor and Bluetooth)PHYSICAL DESIGN AND FABRICATION ISSUESIntroduction of SOC Design and Fabrication flowFloorplanning and Layout considerations Fabrication issues in SOC Design